SI5344B-D-GMR
IC CLOCK MULTIPLIER 44QFN
- 產品分類
- 時脈產生器、鎖相迴路與頻率合成器
- 封裝
- 44-VFQFN Exposed Pad
- 庫存
- 7,740 件
- 供貨狀態
- 當前數量需確認。
產品屬性
| 製造商 | Skyworks Solutions Inc. |
|---|---|
| 產品分類 | 時脈產生器、鎖相迴路與頻率合成器 |
| Differential - Input:Output | Yes/Yes |
| Divider/Multiplier | Yes/No |
| Frequency - Max | 350MHz |
| Input | Clock, Crystal, LVCMOS |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Output | CML, HCSL, LVCMOS, LVDS, LVPECL |
| Package | Tape & Reel (TR),Cut Tape (CT) |
| PLL | Yes |
| Product status | Active |
| Ratio - Input:Output | 4:4 |
| Supplier Device Package | 44-QFN (7x7) |
| Type | Clock Multiplier, Jitter Attenuator |
| Voltage - Supply | 1.71V ~ 1.89V, 3.14V ~ 3.47V |
| 資料表 | 查看資料表PDF |
採購概覽
SI5344B-D-GMR 的主要供貨及採購資訊。
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SI5344B-D-GMR 詳細描述
Product Overview
The Skyworks Solutions Inc. SI5344B-D-GMR is a surface-mount clock multiplier and jitter attenuator IC intended for timing and frequency-synthesis functions. The device integrates one PLL-based circuit and supports a maximum frequency of 350 MHz. It accepts clock, crystal, or LVCMOS input signals and provides CML, HCSL, LVCMOS, LVDS, and LVPECL output formats. The input-to-output ratio is specified as 4:4, with differential input and differential output support. It operates from supply ranges of 1.71 V to 1.89 V and 3.14 V to 3.47 V over a temperature range of -40°C to 85°C. The component is supplied in a 44-VFQFN exposed-pad package with a 7 mm x 7 mm supplier device package.
Key Features
- Clock multiplier and jitter attenuator IC with one PLL circuit.
- Supports clock, crystal, and LVCMOS input types.
- Provides CML, HCSL, LVCMOS, LVDS, and LVPECL output types.
- Operates up to 350 MHz with a 4:4 input-to-output ratio.
- Uses 1.71 V to 1.89 V and 3.14 V to 3.47 V supply ranges.
- Comes in a 44-VFQFN exposed-pad surface-mount package rated for -40°C to 85°C.
Applications
- Timing generation for embedded processors and programmable logic designs.
- Jitter attenuation in local reference-clock distribution paths.
- Frequency synthesis for systems using differential logic interfaces such as LVDS, LVPECL, HCSL, or CML.
- Clock conditioning for equipment that requires LVCMOS or crystal-derived input timing.
Design & Procurement Notes
Designers should verify the required output standard, input source type, and 350 MHz frequency ceiling during timing architecture selection. The specified 4:4 ratio and differential input/output support should be matched to the clock tree topology. Board layout should account for the 44-VFQFN exposed pad and surface-mount assembly, including an appropriate land pattern for the package. Power supply planning must consider both 1.71 V to 1.89 V and 3.14 V to 3.47 V supply ranges. Timing and thermal verification should be performed within the -40°C to 85°C operating temperature range.
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