SI5324C-C-GMR
IC CLOCK MULT 2KHZ-346MHZ 36VQFN
- 產品分類
- 特定應用時脈與時序 IC
- 封裝
- 36-VFQFN Exposed Pad
- 庫存
- 8,594 件
- 供貨狀態
- 當前數量需確認。
產品屬性
| 製造商 | Skyworks Solutions Inc. |
|---|---|
| 產品分類 | 特定應用時脈與時序 IC |
| Differential - Input:Output | Yes/Yes |
| Frequency - Max | 346MHz |
| Input | Clock |
| Main Purpose | Ethernet (WAN), SONET/SDH/STM, Video |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature | -40°C ~ 85°C |
| Output | CML, CMOS, LVDS, LVPECL |
| Package | Tape & Reel (TR),Cut Tape (CT) |
| PLL | Yes |
| Product status | Active |
| Ratio - Input:Output | 2:2 |
| Series | DSPLL® |
| Supplier Device Package | 36-QFN (6x6) |
| Voltage - Supply | 1.71V ~ 3.63V |
| 資料表 | 查看資料表PDF |
採購概覽
SI5324C-C-GMR 的主要供貨及採購資訊。
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SI5324C-C-GMR 詳細描述
Product Overview
The SI5324C-C-GMR from Skyworks Solutions Inc. is an active application-specific clock and timing integrated circuit in the DSPLL® series. It is supplied in a 36-VFQFN exposed-pad package, with a supplier device package of 36-QFN (6x6), and is intended for surface-mount assembly. The device is described for clock/frequency multiplication, jitter attenuation, and multiplexer functions in Ethernet WAN, SONET/SDH/STM, and video timing contexts. It includes one circuit, accepts a clock input, and provides one output with a listed input-to-output ratio of 2:2. The maximum frequency value supplied is 346MHz, and the output interface families listed are CML, CMOS, LVDS, and LVPECL.
Key Features
- Skyworks Solutions Inc. DSPLL® series part SI5324C-C-GMR; lifecycle status Active; PLL listed as Yes.
- Clock/frequency multiplier, jitter attenuator, and multiplexer function for Ethernet WAN, SONET/SDH/STM, and video timing applications.
- One circuit with clock input and one output; input-to-output ratio 2:2; differential input/output Yes/Yes.
- Maximum frequency 346MHz; output families CML, CMOS, LVDS, and LVPECL; supply voltage 1.71V to 3.63V.
- Operating temperature range -40°C to 85°C; 36-VFQFN exposed pad, 36-QFN (6x6), surface mount.
Applications
- Ethernet WAN equipment timing paths that require clock multiplication, jitter attenuation, or clock multiplexing.
- SONET/SDH/STM transport systems requiring jitter attenuation or clock/frequency multiplication.
- Video systems requiring clock/frequency multiplication or multiplexed timing signals.
Design & Procurement Notes
When selecting the SI5324C-C-GMR, verify that the board-level supply can operate within the specified 1.71V to 3.63V range and that downstream logic can accept one of the listed output families: CML, CMOS, LVDS, or LVPECL. Confirm that the design requires a single circuit with clock input, one output, a 2:2 input-to-output ratio, and differential input/output behavior. The 36-VFQFN exposed-pad package and 36-QFN (6x6) supplier device package require a surface-mount footprint appropriate for the exposed pad. The supplied lifecycle status is Active.
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