XCVU35P-2FSVH2892E
IC FPGA 416 I/O 2892FCBGA
- 製造商
- AMD
- 產品分類
- FPGA - 現場可程式化閘陣列
- 封裝
- 2892-BBGA, FCBGA
- 庫存
- 1,411 件
- 供貨狀態
- 當前數量需確認。
產品屬性
| 製造商 | AMD |
|---|---|
| 產品分類 | FPGA - 現場可程式化閘陣列 |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 100°C (TJ) |
| Package | Tray |
| Product status | Last Time Buy |
| Series | Virtex® UltraScale+™ |
| Supplier Device Package | 2892-FCBGA (55x55) |
| Voltage - Supply | 0.825V ~ 0.876V |
| 資料表 | 查看資料表PDF |
採購概覽
XCVU35P-2FSVH2892E 的主要供貨及採購資訊。
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XCVU35P-2FSVH2892E 詳細描述
Product Overview
The AMD XCVU35P-2FSVH2892E is a Virtex UltraScale+ field programmable gate array supplied in a 2892-BBGA, FCBGA package with a 2892-FCBGA (55x55) device package. It provides 416 I/O, 1,906,800 logic elements/cells, 108,960 LABs/CLBs, and 49,597,645 total RAM bits. The device is surface mount and operates from a 0.825 V to 0.876 V supply range, with a specified junction temperature range of 0°C to 100°C.
Key Features
- Virtex UltraScale+ FPGA family designation for the AMD XCVU35P-2FSVH2892E.
- 2892-BBGA, FCBGA package with 2892-FCBGA (55x55) device package.
- 416 I/O.
- 1,906,800 logic elements/cells and 108,960 LABs/CLBs.
- 49,597,645 total RAM bits.
- 0.825 V to 0.876 V supply voltage range.
- 0°C to 100°C operating junction temperature range.
- Surface mount mounting type.
Applications
- Programmable logic for embedded hardware control.
- High-density I/O interfacing on system boards.
- Memory buffering for data paths.
- Reconfigurable hardware for system integration.
Design & Procurement Notes
Designers should confirm that the board power supply can meet the 0.825 V to 0.876 V supply range and that thermal design maintains the junction temperature within 0°C to 100°C. The 2892-BBGA, FCBGA package and 2892-FCBGA (55x55) footprint require sufficient PCB area, fanout, and routing resources for 416 I/O. The available logic cells, LAB/CLB count, and RAM bits should be compared with the target design to ensure the device provides the required programmable resources before finalizing the FPGA choice, and verify package compatibility with the assembly process.
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