NB3N3002DTR2G
IC CLOCK GENERATOR 16TSSOP
- 製造商
- onsemi
- 產品分類
- 時脈產生器、鎖相迴路與頻率合成器
- 封裝
- 16-TSSOP (0.173", 4.40mm Width)
- 庫存
- 2,047 件
- 供貨狀態
- 當前數量需確認。
產品屬性
| 製造商 | onsemi |
|---|---|
| 產品分類 | 時脈產生器、鎖相迴路與頻率合成器 |
| Differential - Input:Output | No/Yes |
| Divider/Multiplier | No/Yes |
| Frequency - Max | 200MHz |
| Input | Clock, Crystal |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature | -40°C ~ 85°C |
| Output | HCSL, LVDS |
| Package | Tape & Reel (TR),Cut Tape (CT) |
| PLL | Yes |
| Product status | Active |
| Ratio - Input:Output | 1:1 |
| Supplier Device Package | 16-TSSOP |
| Type | Clock Generator |
| Voltage - Supply | 3.135V ~ 3.465V |
| 資料表 | 查看資料表PDF |
採購概覽
NB3N3002DTR2G 的主要供貨及採購資訊。
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NB3N3002DTR2G 詳細描述
Product Overview
The NB3N3002DTR2G from onsemi is a surface-mount clock generator IC in a 16-TSSOP package. It integrates a PLL and accepts either a crystal or an external clock input. The device provides differential HCSL or LVDS output and supports a maximum frequency of 200 MHz. With a single circuit, a 1:1 input-to-output ratio, and a 3.135 V to 3.465 V supply range, it is intended for board-level timing paths that require compact, differential clock generation.
Key Features
- onsemi NB3N3002DTR2G clock generator IC in a 16-TSSOP surface-mount package
- Integrated PLL accepts clock or crystal input and provides HCSL or LVDS differential output
- Single circuit with 1:1 input-to-output ratio and maximum frequency of 200 MHz
- Operates from a 3.135 V to 3.465 V supply over -40°C to 85°C
- 16-TSSOP package with 4.40 mm width for surface-mount clock timing designs
Applications
- Board-level clock generation for timing-sensitive digital subsystems
- Differential LVDS or HCSL clock distribution in compact circuit boards
- Reference clock conditioning from crystal or external clock sources
Design & Procurement Notes
Designers should confirm that the 3.135 V to 3.465 V supply and -40°C to 85°C operating range match the board environment. Because the device uses a 16-TSSOP surface-mount package, PCB footprint, land pattern, and assembly process should be reviewed. The input accepts clock or crystal sources, while the output provides HCSL or LVDS differential signals, so output termination and signal integrity requirements should be aligned with the chosen format. The 200 MHz maximum frequency and 1:1 ratio should be checked against the target timing architecture.
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