MT58L64L32FT-10IT
IC SRAM 2MBIT PARALLEL 100TQFP
- 產品分類
- 記憶體 IC
- 封裝
- 100-LQFP
- 庫存
- 2,056 件
- 供貨狀態
- 當前數量需確認。
產品屬性
| 製造商 | Micron Technology Inc. |
|---|---|
| 產品分類 | 記憶體 IC |
| Access Time | 10 ns |
| Clock Frequency | 66 MHz |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 64K x 32 |
| Memory Size | 2Mbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Package | Bulk |
| Product status | Active |
| Series | SYNCBURST™ |
| Supplier Device Package | 100-TQFP (14x20.1) |
| Technology | SRAM - Standard |
| Voltage - Supply | 3.135V ~ 3.6V |
| 資料表 | 查看資料表PDF |
採購概覽
MT58L64L32FT-10IT 的主要供貨及採購資訊。
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MT58L64L32FT-10IT 詳細描述
Product Overview
The MT58L64L32FT-10IT from Micron Technology Inc. is a volatile SRAM memory IC with a 2 Mbit capacity organized as 64K x 32. It uses a parallel memory interface and operates from a 3.135 V to 3.6 V supply. The device is specified for a 66 MHz clock frequency and 10 ns access time, and it is supplied in a surface-mount 100-TQFP (14x20.1) package.
Key Features
- 2 Mbit volatile SRAM capacity organized as 64K x 32 for a 32-bit parallel memory interface.
- Parallel memory interface with 66 MHz clock frequency and 10 ns access time.
- 3.135 V to 3.6 V supply voltage range.
- Operating temperature range of -40°C to 85°C (TA).
- Surface-mount 100-LQFP package, 100-TQFP (14x20.1).
Applications
- Volatile working storage for controllers requiring a 32-bit parallel memory interface.
- Buffered data paths in systems using a 66 MHz clock and 10 ns access timing.
- Memory expansion in 3.135 V to 3.6 V surface-mount hardware.
Design & Procurement Notes
When using the MT58L64L32FT-10IT, verify that the host system can drive a parallel memory interface and that the board layout supports a 100-TQFP surface-mount package. The 3.135 V to 3.6 V supply range should be checked against the system power rail, and the -40°C to 85°C ambient range should be considered for thermal margin. The 66 MHz clock and 10 ns access time require timing alignment with the connected logic. The 64K x 32 organization determines address and data width requirements.
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